Validation of a SEU simulation technique for a radiation hardened 64-bit MIPS processor.
- Paper number
IAC-05-C2.5.03
- Author
Mr. Albert Ferrer Florit, TIMA laboratory (INPG), France
- Coauthor
Dr. Raoul Velazco, TIMA laboratory (INPG), France
- Year
2005
- Abstract
Single event upsets (SEUs) are a potential threat to the reliability of digital circuits in the space environment. They are the result of the impact of high-energy particles with sensitive areas of the processors, and are responsible of transient changes, generally called “bit flips” or “upsets”, in bits of information stored within an integrated circuit. Unlike other radiation effects, SEUs can be caused only by a single particle, that although doesn’t damage permanently the device, it can produce unpredicted consequences ranging from erroneous results to system crashes. To avoid these effects, space agencies have traditionally used radiation hardened processors specifically designed for the space environment. However, the increasing demand of more powerful processors that the new space missions requires, together with the complexity and high cost of a custom design, makes the use of Commercial Off-The-Shelf (COTS) based solutions highly attractive. They rely on advanced commercial technology and the use of hardware and software techniques to reduce the radiation effects. One of the aims of the QLF group is to study new techniques and tools for the validation and hardening of complex processors operating under radiation. Currently the author is working with the first 64-bit radiation hardened processor designed for space applications, that has been developed by HIREC and the Japan Aerospace Exploration Agency (JAXA) for its new satellite programme. It is a modified Toshiba TX49 commercial processor, based on the R4000 MIPS RISC architecture, that includes some typical radiation hardening techniques such as an EDAC (Error Detection and Correction) and a parity bit. One objective is to test some software hardening techniques in this processor. Another objective is to be able to predict with high accuracy, the error rate caused by SEU’s over this processor when it is running any program, without using this program in the radiation tests. This is possible if we combine the results of a static radiation test with the use of a Code Emulation and Upset (CEU) fault injection method applied on the program considered. A static test estimates the sensitivity to SEUs by loading all the storage accessible elements of the processor with a predetermined pattern, whose corruption by SEUs is identified by periodically reading out the exercised memory area and comparing it with the expected values. This provides a very worst-case estimation because when the processor is running a real application, the SEUs can affect its results only when they change the values of registers that, in this instant, have useful information for the program. CEU method is a SEU simulation technique that consists basically in the injection of bit flips into random memory cells at random instants using interrupt requests. Our group has developed a hardware platform to obtain the results of this method in a systematic way. A daughterboard with the processor is inserted into a motherboard with all the features needed to realize also the ground radiation test. Validation of a SEU simulation technique for a microprocessor family architecture enables the study of Software Implemented Fault Tolerance (SIFT) techniques without requiring the use of expensive satellite and ground radiation test experiments. Using previous experiences we expect to present the results of current SIFT techniques applied to this processor family, and the results of a SIFT technique that exploits 64 bits architecture when running 32 bits applications. Therefore this work aims to be a contribution to the current discussion between the use of radiation hardened or COTS solutions.
- Abstract document
- Manuscript document
IAC-05-C2.5.03.pdf (🔒 authorized access only).
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