CDHS Design for a university nano-satellite
- Paper number
IAC-06-B5.7.05
- Author
Mr. Gerard Aalbers, Technical University of Delft (TUDelft), The Netherlands
- Coauthor
Mr. Georgi N. Gaydadijev, Delft University of Technology (TU Delft), The Netherlands
- Coauthor
Mr. Rouzbeh Amini, Delft University of Technology, The Netherlands
- Year
2006
- Abstract
This paper will describe the design of the command and datahandling system (CDHS) for a university nano-satellite named Delfi-C 3. Both the satellite and the CDHS are mainly based on commercial-off-the-shelf (COTS) or space hardware off-the-shelf (SHOTS) components to speed up design and production of the satellite.
The Delfi-C 3 satellite, based on the CubeSat standard, is developed with CubeSat Kit, developed by Pumpkin Inc., as a starting point for the overall design. The decision to use the CubeSat Kit influenced the CDHS, because it also incorporated a Texas Instruments microcontroller that is to be used as on-board computer (OBC). This choice poses its constraints on the design of the satellite in general and the CDHS in particular.
First of all, the limitations that are introduced by the microcontroller that is incorporated have to be overcome or worked around. An example is the difficulty of adding a hot-redundant spare for the OBC as it would involve another flightboard as delivered with the Cubesat Kit, which would simply take too much space in the satellite.
Furthermore, the satellite’s design does not feature a power storage system as most of the satellite’s payloads only need to function in sunlight. This means that the power of the satellite can be disrupted at any moment as the satellite goes into eclipse, which obviously affects the data storage capabilities and the boot procedure of the CDHS.
The boot procedure is directly related to the autonomous capabilities of the CDHS. The design of the CDHS is based upon a distributed architecture which will be interconnected by a single I 2C bus. This implies that in case of a failure of the OBC or databus, the microcontrollers located at the subsystems will have to operate without communication or central supervision.
In addition, the I 2C bus features only very limited error detection and correction capabilities. To ensure less error-prone communications inside the satellite, a protocol layer that deals with error detection and correction has been designed and will be presented shortly in this paper.
The paper will treat all the issues presented above and any other issues that came up during the design, focusing on those due to the constraints posed by the design and redundancy philosophy. The solutions and their rationale will be presented and related to the overall CDHS and satellite design.
- Abstract document
- Manuscript document
IAC-06-B5.7.05.pdf (🔒 authorized access only).
To get the manuscript, please contact IAF Secretariat.