Development and Evaluation of Test Circuit for Spotty Byte Error Control Codes

Paper number

IAC-06-D1.P.2.06

Author

Mr. Takeshi Sasada, Japan Aerospace Exploration Agency (IAT/JAXA), Japan

Coauthor

Dr. Haruhiko Kaneko, Japan Aerospace Exploration Agency (IAT/JAXA), Japan

Year

2006

Abstract

Single event upsets (SEU) due to particularly proton or heavy ions were often observed in spacecraft’s electronics. SEU may cause bit errors on both critical mission commands and valuable mission telemetry data. Especially solid state data recorder (SSR) or mass memory uses a large number of commercial memory devices such as SRAM, DRAM, and EEPROM in the space environment, thus stochastic effect of radiation is inevitable.

To protect onboard data, various fault-tolerant techniques were applied. Most popular one is error control code (ECC). However, conventional ECCs, such as Hamming codes and Reed-Solomon (RS) codes are not necessarily suitable for the memory systems, because Single-bit Error Correcting - Double-bit Error Detecting (SEC-DED) Hamming codes cannot correct random multiple-bit errors. RS codes require a large number e.g., 50 percents at (12, 8) RS code, of check bits. Namely, some redundant memories, i.e., extra power and weight to spacecraft, are essential. Japan Aerospace Exploration Agency (JAXA) has studied a new class of ECC suitable for correcting multiple-bit errors in a byte with appropriate redundant bits, called spotty byte ECC. The spotty byte ECC, the first developed in the world, is also suitable for detecting hardware failures within one memory chip.

The spotty byte ECCs are designed based on parity check matrices, and hence error control capabilities of these codes are mathematically proven. To apply these ECCs for space-use, we have to develop encoders and decoders for the ECCs. We have developed a test circuit of encoders and decoders for three classes of RS codes and for three classes of spotty byte ECCs. The test circuit is designed by Verilog-HDL and implemented on an FPGA. A parallel decoding algorithm is utilized to construct low-latency and high-throughput decoders. Gate counts and clock frequency of these encodes and decodes are evaluated; which revealed that the evaluated encoders and decoders have reasonable complexity with clock frequencies of above 50 MHz. Also, we have evaluated error control capabilities, i.e., user bit error rates (BERs), miscorrection probabilities, and error detection probabilities, of these codes by a series of simulations using the developed FPGA. Simulation result indicates that BER of a spotty byte ECC is a hundred times lower than a RS code having almost same check-bit length.

Abstract document

IAC-06-D1.P.2.06.pdf

Manuscript document

IAC-06-D1.P.2.06.pdf (🔒 authorized access only).

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