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    • highly integrated mmic chipset for ku-band satellite transponder

    Paper number

    IAC-08.B2.5.9

    Author

    Mr. Apurba Bhattacharya, Space Applications Centre (SAC), ISRO, India

    Year

    2008

    Abstract

    Abstract — This paper presents the architecture, design and measured results of high performance multifunction GaAs MMIC chipset for Ku-band satellite payload. Chipset is designed with the objective to achieve best performance with minimum number of highly integrated MMICs and minimum off-chip components. Chipset contains Low Noise Amplifier (LNA), Double Balanced resistive PHEMT mixer (DBM), Variable Gain Amplifier (VGA) and Amplifier with 4-bit digital attenuator. MMICs are realized using 0.2?m GaAs PHEMT process. Key features of these circuits are low noise, excellent gain flatness, LO harmonic rejection and good linearity with gain control. In design, special attention was given to unconditional stability and good matching. This makes all MMICs cascadable, which eliminates isolators in system design. These MMICs reduce complexity and cost of satellite onboard subsystems and provide an ultra miniature, three-chip all MMIC solution to satellite on board receiver design. The three-chip receiver achieves 55dB gain with 1.6dB Noise figure in 13.5GHz-15GHz frequency band. MMIC chips are designed for two standard packages with chip size 2.6mm x 1.6mm and 2.6mm x 2.0mm. Index Terms — Attenuators, MMICs, MMIC amplifiers, MMIC mixers, noise, satellite communication onboard systems.

    (PURPOSE)

    I. INTRODUCTION: Ku-band is a popular frequency band in satellite communication for fixed and broadcast services. There are different sub-bands operating within Ku-band, like (14.00GHz-14.25GHz/ 10.95GHz-11.2GHz), (14.25GHz-14.50GHz/ 11.45GHz-11.70GHz) etc.. To cater satellite transponder requirement covering all these bands four MMICs are designed. These MMICs enable design of satellite on board receiver RF section in minimum size and weight (75g) with lower system cost and minimum manual labor. Designed MMICs integrate several functions in single chip. Active components, presently realized in MMIC are 1) Low Noise Amplifier. 2) Downconverter with Double Balanced Mixer 3) IF Variable Gain Amplifier 4) IF Variable Gain Amplifier with 4bit digital attenuator. Variable Gain Amplifier with analog and digital gain control can be used in channel amplifies also.

    (METHODOLOGY AND TEST RESULTS)

    II. SYSTEM SIMULATION In a top down design approach, first a system simulation is completed using linear and harmonic balance analysis tools. Required specifications of the circuits, derived from system simulation of receiver, are shown in table 1, which are also achieved results. Space qualified MMICs, meeting these specifications are fabricated for satellite payloads of INSAT and GSAT spacecrafts.

    Low Noise Amplifier MMIC: Frequency 13.5-15.0GHz, NF (max.) 1.5dB (test box with isolator), Gain 27dB (Low Bias), Gain Flatness 0.7dB, Input R/L 10dB. Small FFS Double Balanced Downconverting Mixer MMIC: RF 13.5-15.0GHz, LO frequency 2-4GHz, LO power 0dBm, Conv. Gain 6dB, Gain Flatness 0.5dB, LO harmonics -49dBm. IF Variable Gain Amplifier (Analog) and Amplifier With Digital Attn.: Frequency 10.7-12.0GHz, Gain 24-31.5dB (setting range), Gain Flatness 0.2dB, IP3O 24dBm. General: Process 0.2?m PHEMT, Chip count 4MMICs, 1MIC filter for 55dB gain, Cascadable Yes, Cascaded NF 1.6dB (MMIC LNA with input isolator).

    III. LOW NOISE AMPLIFIER: Presently, no off the shelf MMICs are available meeting specifications listed in Table 1. To achieve these specifications a four stage LNA is designed. The circuit is designed for unconditional stability. To meet best possible Noise Figure (NF), input VSWR, gain and gain flatness following design approach is used 1) An optimum PHEMT size [1] is used with series inductive feedback. It requires minimum input matching circuit, thus reducing input circuit loss while maintaining a broad noise figure circle. This configuration is used in first two stages. 2) Small input matching circuit required is incorporated in microstrip line connecting to connector. This provides better noise match with low loss. 3) Controlled feedback is used with series inductive feedback in third and fourth stages to meet stringent gain flatness. Full S-parameter measurement is performed in RFOW (RF On Wafer) test. For noise figure measurement, the chip was mounted in a test box on carrier plate with microstrip line and connector.

    IV. DOWNCONVERTER WITH DOUBLE BALANCED MIXER: Small FFS (Fractional Frequency Shift) [2] MMIC mixers are not available commercially, meeting our specifications. A balanced configuration is selected for this design to improve spurious, LO and LO harmonics rejection, so that stringent filters are not required in system design to prevent saturation of IF amplifiers due to LO harmonics. Balanced mixers need baluns at RF, IF and LO ports. Passive baluns using coupled lines are used in RF and IF port. As LO is in S-band, baluns are difficult to realize in MMIC at this frequency due to their large size. Differential amplifier topology is used as compact active baluns. The mixer circuit contains following six circuits in single chip. 1) RF buffer 2) RF balun 3) Resistive PHEMT quad mixing cell 4) IF balun 5) LO differential amplifier 6) IF buffer Resistive PHEMT is used as mixing device [3]. For the selected size of the mixing cell PHEMT, variation of Rds with Vg is calculated. This gives an estimate of On and Off resistance of PHEMT and LO voltage swing required. A differential amplifier is used to obtain this voltage swing from 0dBm LO input. Test results are shown in table. In-band spurious is better than 77dBc with –30dBm RF input (approx. 5dB gain of RF buffer with passive balun precedes mixing cell). Mixer operates in full Ku-band and it can cater for any LO frequency in 2GHz-4GHz range.

    V. VARIABLE GAIN AMPLIFIER: To meet the specifications of VGA listed in table 1, following circuit configuration is chosen 1) First stage is a low noise design. 2) Second stage is variable gain stage using two-cell cascode distributed amplifier [4]. It achieves gain control maintaining return loss, IP3O and positive gain slope with frequency. Gain is controlled by gate bias of CG device. 3) Third stage and fourth stage are controlled feedback stage to achieve gain flatness, return loss and linearity. All the stages are designed to be unconditionally stable. Chip photo of IF VGA shows these circuit elements.

    VI. VARIABLE GAIN AMPLIFIER WITH DIGITAL CONTROL: This circuit consists of following sub circuits 1) 4-bit Digital attenuator block 2) Control feedback in following two stages Attenuator with series and shunt switch is used here [2].

    VII. CAD SIMULATION, FABRICATION AND TEST: The designed circuits are simulated using ADS 2002TM. Schematic, generated from layout, was used for simulation. DRC and extraction is done in CADENCETM. Extracted circuits are re-simulated in PSPICETM. Layout design considers RF On Wafer measurement ease. Simulated yield with specified RF performance was 85Designed circuits were fabricated using ED02AH PHEMT process of OMMIC, Limeil-Brevannes, France. RF On Wafer measurement was done using cascade RF probes. All chips with good dc measurement showed excellent RF performance. DC to RF yield of all the circuits is almost 100

    VIII. CONCLUSION: In this paper we have demonstrated the design, simulation and test results of four key circuits of Ku-band communication satellite payload using GaAs MMIC technology. Designed MMICs are used in a receiver and demonstrated excellent performance of 52dB gain, 1.6dB NF and 22dBm TOI, meeting stringent spurious requirement. Special care is taken in mixer design to keep the LO harmonic level low at IF output (like, 2.8GH x 4=11.2GHz, which is only 250MHz away from IF 11.45GHz). Variable Gain Amplifier (analog) is used to compensate cumulative gain variation of all circuits over temperature. This paper demonstrates several new approaches in satellite payload design, like, use of ultra Low Noise MMIC LNA, Variable gain amplifier for temperature compensation of gain, and mixers with low LO harmonic level. These simplify on board receiver design considerably

    ACKNOWLEDGEMENT: Authors are thankful to OMMIC staffs, Limeil-Brevannes, France, for their valuable suggestions and A. Banik, SAC, for interface with foundry regarding DRC, RFOW test and packaging. Authors are also thankful to Director, SAC for his constant encouragement.

    REFERENCES: [1] Brian Hughes, “Designing FETs for Broad Noise Circles,” IEEE Trans. Microwave TheoryTech., vol. 41, no. 2, pp. 190-198, February 1993. [2] I. D. Robertson, S. Lucyszyn, RFIC and MMIC design and technology, London: The Institution of Electrical Engineers, 2001. pp 484-485365-373 [3] S. A. Maas, “A GaAs MESFET mixer with very low intermodulation,” IEEE Trans. Microwave TheoryTech., vol. 35, no. 4, pp. 425-429, April 1987. [4] Kennan W., Andrade T and Huang C. C., “A 2-18GHz monolithic distributed amplifier using dual-gate GaAs FETs,” IEEE Trans. Microwave TheoryTech., vol. 32, no. 12, pp. 1693-1697, December 1984. [5] C. Yuen, et. al., “A miniature 17/12 GHz MMIC receiver for satellite communication.,” 1995 IEEE MTT-S Int. Microwave Symp. Dig., pp. 961-964, 1995. [6] Jin-Cheol Jeong, et. al., “Development of Ku-band receiver/ downconverter for satellite transponder,” 2002 IEEE MTT-S Int. Microwave Symp. Dig., pp. 1257-1260, 1995.

    Abstract document

    IAC-08.B2.5.9.pdf

    Manuscript document

    IAC-08.B2.5.9.pdf (🔒 authorized access only).

    To get the manuscript, please contact IAF Secretariat.