Systemsimulation of the university microsatellite Flying Laptop and implementation of an FPGA-based On-board Computer Simulator
- Paper number
IAC-08.B4.6.A5
- Author
Mr. Albert Falke, University of Stuttgart, Germany
- Coauthor
Mr. Toshinori Kuwahara, University of Stuttgart, Germany
- Coauthor
Mr. Yasir Muhammad, Institute of Space Systems, Universität Stuttgart, Germany
- Coauthor
Dr. Jens Eickhoff, Astrium GmbH, Germany
- Coauthor
Prof. Hans-Peter Roeser, University of Stuttgart, Germany
- Year
2008
- Abstract
The Flying Laptop is the first satellite of the Stuttgart Small Satellite Program, which is under development by the Institute of Space Systems (IRS) of the Universität Stuttgart. It has a mass of about 120 kg and is the innovative test bed for an on-board computer (OBC) which is based on a field programmable gate array (FPGA). The mission objectives are to demonstrate new technologies such as a FPGA-based OBC, an electrical solar panel deployment mechanism and several COTS components. The scientific objectives enclose earth observation with three different payload camera systems. Since a couple of years renowned satellite manufacturers utilize special simulation and test technologies to guarantee mission success from the beginning of a space project. The Model-based Development and Verification Environment (MDVE) is one of these infrastructures. It has been developed by EADS Astrium Satellites in Friedrichshafen, Germany. MDVE supports spacecraft development, on-board software verification and spacecraft design validation. Major benefit of model-based system development applying MDVE is the early possibility for simulated satellite mission operations, using real on-board software in the virtual satellite, even before availability of real hardware. The implementation of a system simulation environment for the complete satellite system is new to microsatellite projects, but is applied in the Flying Laptop development process due to an MDVE installation at the IRS - sponsored by EADS Astrium. Using this infrastructure each satellite component is represented by a separate model in order to constitute the whole satellite system into the simulator. It must be mentioned in particular, that as a new development the FPGA-based on-board computer system is also to be reflected in the spacecraft simulation. This is achieved by an on-board computer FPGA-board model running in parallel to the real-time simulator. By connecting the simulator with the on-board control algorithms, executed on the FPGA-based on-board computer, a closed-loop simulation setup is accomplished. Goal of this paper is to point out the system simulator setup, the developed test benches, their capabilities and benefits for the microsatellite development process. Special focus is given to the modeling of the FPGA-based on-board computer simulator. The developed test bed ends up in an outstanding development environment for the on-board control algorithms, which is used intensively for algorithm functional verification. The paper is completed by demonstration of some simulation results achieved during optimization of power management and attitude control system algorithms.
- Abstract document
- Manuscript document
(absent)