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  • Using Reconfigurable Hardware for Routing in Mesh Networks of Small LEO Satellites

    Paper number

    IAC-10.B4.6A.10

    Author

    Mr. Aimal Siraj, void inc., Japan

    Coauthor

    Ms. Yukie Yashiro, Japan

    Coauthor

    Dr. Toshiaki Iwata, National Institute of Advanced Industrial Science of Technology (AIST), Japan

    Year

    2010

    Abstract
    Routing in mesh networks comprised of LEO (low Earth orbit) satellites is desirable due to the short duration during which any single satellite can establish a link with a ground station. But due to their size, small satellites have restrictions on computation resources, memory space, and available power. In this paper we explore implementing a routing algorithm for use on-board small LEO satellites, using reconfigurable hardware. The routing algorithm we use employs snapshot information to determine how to route data under the constant dynamic conditions of such a network. It also contains features for implementing fault-tolerance, and data prioritization based on time, location, or type of the en route data. We show how to implement such an algorithm using a modular architecture, where the design as well as its performance are independent of parameters determined by the mesh network topology. These parameters include but are not limited to, the number of inter-satellite links (ISLs) per satellite, the snapshot interval, and the number of satellites in the whole network. We implement our design in a COTS FPGA (Commercial, off-the-shelf Field Programmable Gate Array) and determine its required logic and memory resources for variations in the different parameters. In addition, we also program these designs into an FPGA board (based on the same device), and measure its power requirements for each parameter change. To measure the dynamic power under actual traffic load though, we connect a number of these FPGA boards as a grid emulating a neighborhood of satellites, and connect PCs to the edges of this grid to generate and monitor traffic flow. We conclude our paper by summarizing the FPGA logic and memory resources, and the static and dynamic power requirements of such a routing scheme based on variations in mesh network topology.
    Abstract document

    IAC-10.B4.6A.10.brief.pdf

    Manuscript document

    IAC-10.B4.6A.10.pdf (🔒 authorized access only).

    To get the manuscript, please contact IAF Secretariat.