• Home
  • Current congress
  • Public Website
  • My papers
  • root
  • browse
  • IAC-11
  • B2
  • 2
  • paper
  • Development of the Telemetry Transmitter for the Small Satellite Flying Laptop

    Paper number

    IAC-11,B2,2,1,x11267

    Author

    Mr. Ulrich Beyermann, University of Stuttgart, Germany

    Coauthor

    Prof. Hans Peter Roeser, University of Stuttgart, Germany

    Coauthor

    Mr. Max Spetzler, Germany

    Year

    2011

    Abstract
    The telemetry, tracking and control (TT&C) system of a satellite is one of the critical systems for the success of a mission. If data transmission from or to the satellite is not possible, the mission is lost. Therefore, the system has to be as reliable as possible. It has to be guaranteed that either no failure occurs during lifetime or that the system is tolerant to failures. Following the trends in the space market the TT&C system of the Flying Laptop (FLP) will be developed as a Software Defined Radio (SDR), moving most of the signal processing to the digital domain, e.g. the modulation. In commercial terrestrial applications SDRs are state of the art. Therefore, the challenge in developing such a system lies in the adaption of available concepts to the high demands concerning reliability and availability inherent to space systems.
    
    This Paper describes the transmitter part of the FLP TT&C system. The objectives for this system are: high reliability with one failure tolerance, flexibility by using a reprogrammable computing element, low power consumption including a power down mode and lower costs compared to an industrial standard TT&C system. Additional requirements are the use of ham radio frequencies, data rates up to 100 kbps, omnidirectional transmission and compatibility to ESA communication standards.
    
    These objectives lead to a system design based on an Actel Flash FPGA as central computing element. Despite its good performance it has never before been flown in a system critical application. The baseband analogue signal is generated with a high-speed digital-analogue-converter (DAC) which runs at lower speed to have some performance margin for increased reliability. The system is completed with a frequency mixer which transfers the signal to S-band, a bandpass filter for frequency selection, a power amplifier and an isolator before the output to the dipole antenna.
    
    With the boundary conditions and parts mentioned above, a first engineering model is built. Tests proved the functionality of the whole system both in analogue and digital signal processing. Link budget calculations with a variety of orbits and antenna simulations were used to ensure the required performance of the system.
    Abstract document

    IAC-11,B2,2,1,x11267.brief.pdf

    Manuscript document

    IAC-11,B2,2,1,x11267.pdf (🔒 authorized access only).

    To get the manuscript, please contact IAF Secretariat.