GR712RC – A Dual-Core Processor for Demanding Space Applications
- Paper number
IAC-11,C2,8,4,x10345
- Author
Mr. Sandi Habinc, Aeroflex Gaisler, Sweden
- Year
2011
- Abstract
The GR712RC integrated circuit is a first of its kind, offering the space community powerful multi-core processor capability in combination with multiple SpaceWire and CCSDS telemetry and telecommand communications links. The device is highly configurable and can operate in many different applications, ranging from platform control to payload processing. The main functions of the GR712RC integrated circuit are: \begin{itemize}2 x LEON3FT 32-bit SPARC V8 Processor\item \end{itemize} \begin{enumerate}IEEE-754 High-performance Floating Point Unit for each processor\item \end{enumerate} \begin{enumerate}SPARC V8 Reference Memory Management Unit for each processor\item \end{enumerate} \begin{enumerate}4x4kByte Instruction Cache, 4x4kByte Data Cache for each processor\item \end{enumerate} \begin{itemize}Debug Support Unit with JTAG Debug Interface\item \end{itemize} \begin{itemize}6 x SpaceWire links, of which two with RMAP\item \end{itemize} \begin{itemize}10/100 Mbit/s Ethernet MAC\item \end{itemize} \begin{itemize}Redundant Mil-Std-1553B BC/RT/MT (A/B)\item \end{itemize} \begin{itemize}2 x CAN 2.0B, I2C and SPI interfaces\item \end{itemize} \begin{itemize}8 x Timers, 6 x UARTs, Interrupt Controller, General Purpose Input/Output\item \end{itemize} \begin{itemize}CCSDS/ECSS Telemetry and Telecommand\item \end{itemize} \begin{itemize}192 kByte On-chip SRAM with ECC\item \end{itemize} \begin{itemize}Memory controller for SRAM/PROM/SDRAM/IO with BCH and RS protection\item \end{itemize} The performance of the GR712RC device at 125 MHz system clock frequency is expected to be approximately 300 Dhrystone MIPS, and the data rate of the SpaceWire links is above 200 MBPS. The GR712RC device is a dual-core processor, with advanced interface protocols, dedicated for high reliability radiation-hard aerospace applications. The GR712RC is fabricated at Tower Semiconductors Ltd., using standard 180 nm CMOS technology. It employs radiation-hard-by-design methods from Aeroflex Gaisler and the RadSafe technology from Ramon Chips Ltd. As a preparation for this development, a first silicon prototype, the GR702, with integrated processor and SpaceWire interfaces has been successfully manufactured, validated and undergone radiation testing. The GR712RC device has been designed to be latch-up free, to be fully protected against single event upsets in registers and memory, and to tolerate a high total ionizing dose. The GR712RC will undergo similar radiation tests as its predecessor. The full paper will provide an overview of the GR712RC device, its various functions and their application in the space domain; it will also cover the mitigation techniques used against space environment effects, encompassing both the design methods and the incoming irradiation test results.- Abstract document
- Manuscript document
(absent)