FENICE: a Flexible, Scalable High Performance Satellite AIS receiver
- Paper number
IAC-13,V,3-B2.8,7,x20259
- Author
Mrs. Veronica De Perini, CGS S.p.A.Compagnia Generale per lo Spazio, Italy
- Coauthor
Mr. Andrea Di Cintio, CGS S.p.A.Compagnia Generale per lo Spazio, Italy
- Coauthor
Mr. Alberto Ginesi, European Space Agency (ESA), The Netherlands
- Coauthor
Prof. Giulio Colavolpe, National Interuniversity Consortium for Telecommunications (CNIT), Italy
- Year
2013
- Abstract
The ESA-CGS co-funded FlexiblE inNovative AIS reCeiver prototypE (FENICE) project aims at developing a Satellite AIS receiver prototype, able to decode and detect the AIS messages transmitted by the ships covered by the Antenna FoV of an AIS LEO satellite, fully compatible with both existing and future AIS terrestrial transponders. The proposed implementation is fully flexible and covers both the case of on-ground and on-board processing, as well as the deployment of different antenna subsystems. The trade-off on-board versus on-ground processing was analysed through further verification of the complexity and performance of the two options. The design and development of the prototype allowed assessing in detail the performances and complexity of the receiver. A dedicated Test Bed, able to generate the required AIS signals, was also developed. An approach based on 3U cPCI COTS boards has been selected for prototype implementation. The architecture includes: - an RF-IF Module, composed by: o RF-IF Front-End (developed from scratch, hosting the Analog-to-Digital converters); o Digital I/O (based on CGS-proprietary general-purpose board, performing digital signal conditioning and buffering); o Radio Frequency Generator (providing Local Oscillators and master clocks). - a Digital Module, an FPGA Board equipped with target Virtex5 device (selected among those having a space-grade counterpart), for VHDL implementation of the advanced demodulation algorithms - a Host Computer, for prototype management and Test Bed interface. The assessment of the performance and complexity of the processing was achieved by implementing on target FPGA the enhanced algorithms and technologies originally proposed by ESA, and further improved during the FENICE project. Thanks to the innovative demodulation algorithms and architecture, FENICE demonstrated to outperform all the known space-based AIS receivers. Furthermore, the FENICE AIS P/L accommodation on board mini- and micro-satellite platforms has been explored, providing initial engineering budgets (mass, volume, power consumption) to support SAT-AIS system studies. The analysis considered different antenna subsystems, including the CGS-led VHF Miniaturized Antenna project under ESA ARTES 5.1 program. This paper provides an overview of the main achievements and results of the FENICE project for the several configurations analysed in terms of architecture, antenna subsystem and satellite platform. The results demonstrated that the FENICE receiver provides an excellent solution both in terms of signal processing and in terms of technology to cope with the extremely challenging C/I expected over the AIS channels as seen from the satellite.
- Abstract document
- Manuscript document
(absent)