A Novel Implementation of Beacon Receiver using FPGA
- Paper number
IAC-16,B2,2,6,x32953
- Coauthor
Mr. Kalpataru Sharma, Indian Space Research Organization (ISRO), India
- Coauthor
Mr. K. Rathnakara, Indian Space Research Organization (ISRO), India
- Coauthor
Mr. Sathyanarayana Raju, Indian Space Research Organization (ISRO), India
- Coauthor
Mr. H.V. Lokesha, Indian Space Research Organization (ISRO), India
- Year
2016
- Abstract
Beacon receiver is an important part of the ground segment in satellite technology. This paper presents a software defined radio based digital beacon receiver. The beacon receiver is developed on Xilinx FPGA. The objective of the project was to develop a cost effective solution with good power estimation accuracy. In order to achieve this goal the direct IF digital processing strategy is used, this allows eliminating the preprocessing requirement resulting in saving DSP resources. Around 55% of DSP resources were saved by using this strategy. The objective of DSP algorithm is to deliver a real time solution. To achieve this goal a DSP algorithm is developed by utilizing the available unused temporal bin slot efficiently. This novel implementation avails band of interest to user with a good agreement of frequency resolution with a throughput of 14 ms . The receiver is developed for the planned usage of satellite tracking, auto uplink power control, Channel noise floor monitoring, propagation channel study and spectral analysis. The key issues related to beacon receiver are addressed and possible optimum solutions are suggested in paper. While providing a cost effective solution the quality of the system is maintained as well. Performance of the receiver is verified under various operating conditions and the results are presented in paper. The tests confirm good performance of the receiver with satisfactory estimation accuracy of around .01 dB and improved operating threshold.
- Abstract document
- Manuscript document
(absent)