Parallelizing Radar signal processing for space situational awareness in the GESTRA system – A hybrid approach
- Paper number
IAC-19,A6,IP,3,x51979
- Author
Mr. Christoph Reising, Germany, Fraunhofer FHR
- Coauthor
Dr. Robert Kohlleppel, Germany, Fraunhofer FHR
- Coauthor
Mr. Helmut Wilden, Germany, Fraunhofer FHR
- Coauthor
Dr. Nadya Ben Bekhti, Germany, Fraunhofer FHR
- Coauthor
Dr. Andreas Brenner, Germany, Fraunhofer FHR
- Coauthor
Dr. Thomas Eversberg, Germany, DLR (German Aerospace Center)
- Year
2019
- Abstract
The most actual radar systems perform the signal processing on either CPU, FPGA or GPGPU-level. The main steps of the processing-chain are pulse compression, Range-Doppler compression, multi-pulse signal integration and techniques to suppress multi-detections of the same target. For the challenging application of space surveillance, there are many possibilities for range and Doppler values. The resulting FFTs do not fit in a single GPU or FPGA-RAM, making the use of a single GPU or FGPA impossible. Facing these requirements, one solution is the use of a hybrid GPU- and CPU-Cluster system where the strength of the included processing architectures is used. This paper presents the handling of these challenges as applied within the project GESTRA (German Experimental Space Surveillance and Tracking Radar). After a short demonstration of the processing-chain, we are presenting an overview of the search-space extent and the influence of the tradeoff between straddle loss and computation time for the coherent integration case. For real-time processing and very low straddle loss acceptance, this results in the use of multiple GPUs using OpenACC and CUDA for the Range-Doppler Compression and multi-pulse signal integration. To avoid cross-talk of different GPUs which is a bottleneck in performance it is advisable to use some CPU time to do several post processing steps simultaneously. This paper also discuss which parts of the processing should be addressed to the GPU- and which to the CPU parts of the processor to achieve the best increase in performance. In conclusion, this paper reveal that an optimal parallelized implementation drastically reduces the computation time of the whole processing-chain compared to a typical CPU-only or GPU-only implementation.
- Abstract document
- Manuscript document
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