FRAMEWORK REFINEMENT PROPOSAL RELATIVE TO FPGA COTS
- Paper number
IAC-19,D1,5,x53290
- Year
2019
- Abstract
This paper presents the development of a framework to assist the component engineer in a process of choosing fault-mitigation techniques in electronic integrated circuits, such as COTS-FPGA (Commercial Off-the-shelf). These failures are due to the effects of spatial radiation, which cause errors in the logical part of a circuit, such as the Single Event Effect (SEE). In the literature on the application of these components, especially in nanosatellites, high processing rates, low energy consumption and low cost are required. Another essential requirement is spatial qualification, that is, hard or radiation tolerant component. To overcome the failures, mitigation techniques are used, which are incorporated in the circuits, by hardware or software. In a recent article researched in the literature, with emphasis on SEE, it is observed the presentation of a sequential, didactic framework with a flow of information relevant to the correct selection of these techniques. However, there was not enough scope (only three techniques) to establish a more detailed comparison of them, presenting partial results. These "hardened" COTS frameworks must undergo continuous improvement processes, as they have an important cost reduction advantage for projects. A COTS FPGA can cost up to twenty times less and can absorb additions in your circuits and logic of operation ("hardening"). It should also be considered that devices manufactured with radiation tolerance may undergo a commercial embargo procedure. However, the selection process should be as complete as possible, allowing the electronic device to function properly in the hostile environment of the space. The COTS, as they were not manufactured for the radiation environment, must be submitted to efficient mitigation processes, observing factors such as: maximum power use, maximum failure rate and minimum required life time. The proposed article covers more mitigation techniques in the SEE framework, considering that the current article has limitations. In addition to the possibility of doubling the number of techniques, the study was carried out over a longer period of seventeen years. With the implementation of these measures, the component engineer can use this tool to design projects in the COTS FPGA area, with the improved mitigation of the effects of radiation, according to the parameters of the mission and greater added knowledge. Keywords: COTS-FPGA, fault mitigation techniques, framework, refinement proposal- Abstract document
- Manuscript document
(absent)