Flexible High-Performance PPC On-Board Computer Architecture based on Silicon-on-Insulator Technology

Paper number

IAC-07-D1.I.07

Author

Mr. Sebastian Ivars, Technical University of Munich, Germany

Coauthor

Wolfram Glauert, Germany

Coauthor

Juergen Frickel, Unknown

Coauthor

Jan Ortner, Germany

Coauthor

Bernd Kandler, Germany

Coauthor

Jehangir Zaman, Germany

Coauthor

Herbert Müller, Germany

Coauthor

Hans-Rainer Graf, Germany

Coauthor

Frank Fleischmann, Germany

Coauthor

Udo Pfingst, Germany

Coauthor

Mr. Michael Schiffner, Technical University of Munich, Germany

Coauthor

Prof. Ulrich Walter, Technical University of Munich, Germany

Year

2007

Abstract

The Institute of Astronautics at the Technical University at Munich in cooperation with space companies and research partners is currently developing a high-performance on-board computer system entirely made of components of the shelf including real-time error correction. Aimed applications are space bus or payload computation which demand large amounts of computing performance like real-time video compression, multi- or hyper spectral data and SAR processing, or security connections with high reliability like loop control, etc.

The hardware architecture is set up of three PowerPC SoI computers which are linked by a majority voter. The Silicon-on-Insulator technology ensures radiation-hardness of the CPUs against Single-Event Latch-Ups, while the triple voting system detects and corrects Single-Event-Upset errors. A majority decision on all redundant CPU prohibits error propagation to the rest of the system. This includes errors from corrupted program code, which would normally result in certain failure. Unlike software correction, which needs coding and encoding phases, this hardware correction works instantly. All type of errors are not visible for the rest of the system, which is essential for critical and security applications.

The architecture has the flexibility to act either as a single system with 3 redundant CPUs with a high reliability through majority voting or it acts as a parallel system in which 3 CPUs operate on different task queues without voting but optimized for extreme data throughput such as real-time video processing.

The system is designed to be transparent and to treat the CPUs in a modular way. The system may be upgraded to compatible new state-of-the-art CPUs by just changing the interfaces and preserving the main logic of the system. Since all parts consist of components-off-the-shelf, the manufacturing is independent from market regulations or supplier bottle-necks.

Besides other interfaces the architecture includes a SpaceWire interface as very performant network solution. SpaceWire is designed to build large, reliable and scalable networks for space applications. Furthermore since it is introduced by the ESA as the new European network standard, many compatible space modules will be available. Thereby complex solutions can be realized by just plugging payloads, actuators and sensors together.

The paper will describe the design of the architecture and the status of the prototype currently under development, as well as concepts for future industrial solutions.

Abstract document

IAC-07-D1.I.07.pdf

Manuscript document

IAC-07-D1.I.07.pdf (🔒 authorized access only).

To get the manuscript, please contact IAF Secretariat.