System Design of the Small Satellite Flying Laptop, as the Technology Demonstrator of the FPGA-based On-board Computing System
- Paper number
IAC-07-B4.6.08
- Author
Mr. Toshinori Kuwahara, University of Stuttgart, Germany
- Coauthor
Dr. Felix Huber, Steinbeis Transferzentrum Raumfahrt, Germany
- Coauthor
Mr. Michael Lengowski, University of Stuttgart, Germany
- Coauthor
Mr. Sebastian Walz, University of Stuttgart, Germany
- Coauthor
Mr. Georg Grillmayer, University of Stuttgart, Germany
- Coauthor
Mr. Albert Falke, University of Stuttgart, Germany
- Coauthor
Prof. Hans-Peter Roeser, University of Stuttgart, Germany
- Year
2007
- Abstract
The goal of this paper is to describe the system design of the small satellite Flying Laptop which is developed by the Institute of Space Systems at the Universität Stuttgart within the Stuttgart Small Satellite Program. The Flying Laptop with a mass of about 120 kg is the test bed for an on-board computer (OBC) with a reconfigurable, redundant and self-controlling high computational ability which is based on a field programmable gate array (FPGA). The functional system architecture design and its implementation onto the hardware in relation to the operational scenario is to be emphasized. The main mission objectives of the Flying Laptop are to demonstrate new technologies such as a FPGA-based OBC, an electrical solar panel deployment mechanism and several COTS components as the first satellite of this program. Besides these objectives the Flying Laptop performs scientific earth observation with three different payload camera systems. The attitude control system with pointing knowledge of better than 7 arcseconds makes it easy to achieve maximum ground sample distance of 25m, and the high speed communication channel in Ka-band up to 500 Mbit/s allows enough data transfer budget, which is exceptional for small satellites. The OBC of the Flying Laptop consists of four central processing nodes and one Command Decoder and Voter (CDV). Both of these are FPGA-based and the nodes are re-configurable during on-orbit operation. The nodes can also be loaded with a soft-core of a microprocessor so that third parties can verify their own software in a “Rent-a-Sat” mode in orbit. The Flying Laptop introduces a conservative design using a CDV which selects the master node from the four nodes. Because this design is based on the assumption that the each of the four nodes performs the exact same tasks at the same time, all input/output signals, in total more than 200 lines, from peripheral electronics are connected in parallel. Due to the demands of peripheral electronics the interfaces of RS422, LVDM, M-LVDS, TTL and I2C are implemented. Furthermore, a mock-up model of the whole satellite in its original size is developed in order to design the mechanical interface and the harness system in actual integration environment. The introduced operational scenario, especially the initial operation and safe mode definition, which is presented in the paper, ensures the validity of the system design.
- Abstract document
- Manuscript document
IAC-07-B4.6.08.pdf (🔒 authorized access only).
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