Hardening by design the CAN module for FPGA applications
- Paper number
IAC-07-C2.6.08
- Author
Mr. Alejandro Salado Diez, Universidad Politécnica de Valencia, Spain
- Year
2007
- Abstract
This paper will present a technique for hardening by design a CAN transceiver module for Field Programmable Gate Array (FPGA) applications which will be tested in-flight onboard the SSETI European Student Earth Orbiter (ESEO) as a part of the RADMEM payload, a system for measuring Single Event Effects on memory chips. Being low-cost its main achievement, the considered FPGAs are of commercial type. Hardening is implemented for soft errors such us Single Event Upsets at gate level in VHDL. As an overview, two techniques are mainly implemented: 1. Triple Modular Redundancy (TMR) 2. Huffman codes Using both of them is possible not only to detect an error but to correct it automatically. Huffman encoders and decoders are implemented in hardware and will code data to be stored in registers and decode it when reading operations. TMR is used at gate level for detecting the soft-errors and correcting them based on multiplexing feedback. Results on performance based on simulations will be published as conclusions for this paper.
- Abstract document