FPGA Implementation Of A High Throughput Error Correcting Tele-command Decoder
- Paper number
IAC-16,B2,8-GTS.3,9,x34173
- Coauthor
Mr. Rakshith Ramesh, India
- Year
2016
- Abstract
The paper provides the implementation of the CCSDS suggested (63, 56) BCH code for tele-command decoder. The (63, 56) code is a modified BCH code which has the advantage of Single Error Correction and Double Error Detection (SECDED). The implementation is memory efficient, has high throughput and zero latency. On an FPGA it is implemented by the use of Look-Up Tables (LUTs). The LUTs are generated based on the specific generator polynomial of the code being used. The working principle behind the implementation is to store the GF (64) elements of the Parity Check Matrix as binary vectors. By doing so the matrix multiplication gets reduced to binary multiplication. This reduces the logic gates utilization in the FPGA.
- Abstract document
- Manuscript document
IAC-16,B2,8-GTS.3,9,x34173.pdf (🔒 authorized access only).
To get the manuscript, please contact IAF Secretariat.