Multifunctional software-defined radio chip designed for small satellite applications

Paper number

IAC-19,B4,6A,5,x51879

Author

Mr. Pedro Rodrigues, Portugal, Tekever

Coauthor

Mr. Tiago Pinto, Portugal, Tekever

Coauthor

Ms. Aleksandra Nadziejko, Portugal, Tekever

Coauthor

Mr. José Magalhães, Portugal, Tekever

Coauthor

Mr. Tiago Ressurreicao, Portugal, Tekever

Coauthor

Mr. Rui Marques, Portugal, Tekever

Coauthor

Mr. Hugo Cruz, Portugal, Tekever

Coauthor

Dr. Sergio Cunha, Portugal, Tekever

Coauthor

Mr. Diogo Matos, Portugal, University of Aveiro

Coauthor

Prof. Nuno Borges Carvalho, Portugal, University of Aveiro

Year

2019

Abstract

Humanity is currently witnessing a modern space race promoted by private companies impelled by cutting-edge technologies and fewer constraints required to access space. This results in the development of reduced-size components and satellites that demand less time from manufacturing to launch. Therefore, all efforts are increasingly focused in achieving compact technologies that match the demanding satellite standards from this Newspace age.

Following this trend within the space communications field, some technological gaps are emerging and waiting to be filled in order to provide compact and robust technologies aligned with current demands that have been pushing forward to increase the level of integration in electronic circuits. Hence, it is now possible to replace a software-defined transceiver tailored to the CubeSat standard by a single chip. Although the main functionality of this transceiver is to offer inter-satellite and ground links in S-band, it is also capable of providing ranging, synchronization, positioning and networking functions. By integrating all components of the transceiver in a single chip, it will facilitate and speed up integration, test and qualifications processes which represent major challenges faced by the ever-evolving small satellite market. In addition, this chip prototype will take into account space agencies requirements so that a final version can be certified to comply with major space standards and withstand the space environment.

Due to the highly complex tasks involved in manufacturing a single transceiver die, the proposed chip consists in a System-in-a-Package enclosing two dies: one regarding the digital and mixed signal processing module and another for the RF front-end. Integrating the transceiver in a single chip offers the opportunity to formulate an improved architecture that provides communications within a broader frequency spectrum thus enabling its use for different applications. Therefore, the RF front-end of this chip is designed to communicate from 300 MHz to 6 GHz (C band), offering the possibility to perform an external up/down-conversion to/from 40 GHz (Ka band).

This paper presents a high-level architecture of the chip detailing all modules and components required to offer the aforementioned functionalities and expected performances. The development process that was defined is also explained and all technical trade-offs are presented to justify the proposed architecture. Additionally, the context around the project is included, both in terms of target applications and certification and qualification of the component for space use.

Abstract document

IAC-19,B4,6A,5,x51879.brief.pdf

Manuscript document

IAC-19,B4,6A,5,x51879.pdf (🔒 authorized access only).

To get the manuscript, please contact IAF Secretariat.